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RTL blocks description in VHDL and Verilog.
IPs Integration like DesignWare, USB, PCI.
Microprocesseur ARM7/9 IPs : DMA... |
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RTL blocks description in VHDL and Verilog.
IPs Integration like DesignWare, USB, PCI.
Microprocesseur ARM7/9 IPs : DMA... |
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Simulation environment creation, testbenches development and writing of tests for IPs or Top Level in VHDL or C.
NCsim
Modelsim
Co-vérification Hardware Axis (Verisity / Cadence)
ZeBu Speed up simulation time for gate level for instance and creation of test platform for software integration team, Firmware, L1 development ... |
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Scan insertion Design Compiler and Physical Compiler ATPG Tetramax
Inscan : scan insertion AMSAL : ATPG TPLG : Protocols Extension TASS : testbench and tester file generator FCON : functional test DUMP file conversion into patterns
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Synthèse Design Compiler STA Primetime Preuve formelle Formality
Ambit
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Floorplanning & Place Physical Compiler Routing ASTRO Extraction Star RC-XT
Virtuoso
DRC & LVS Calibre |
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