Since April 2006 : TI Villeneuve-Loubet

In charge of DFT activity for a mega-module from specification to patterns delivery.

2005-2006 9 month : PHILIPS Sophia-Antipolis
DFT Team

In the DFT Team, I worked for different project, on scan insertion, ATPG, BIST, BISTAR, functional test, analog block test, functional and gate level simulation… I follow the test production in collaboration with test engineers.

2005 : 1.5 month PHILIPS Sophia-Antipolis
Bluetooth division

I built simulation environment for FPGA prototyping. I also used FPGA implementation flow, Synplify QuartusII.

2005 : 5 month Mitsubishi/Renesas Rennes

In a EDGE Digital Base-Band team, I worked on design validation. I worked on simulation environment and I developed test benches and I wrote system tests.
I developed also drivers for Firmware.

2004 : 6 month STMicroelectronics Crolles

In a physical implementation team I performed synthesis and I worked on Back-end flow for HCMOS9 and CMOS90. I also worked on DFT scan insertion and ATPG.

2004 : 3 month STMicroelectronics Sophia-Antipolis

Cellular Infrastructure Division
Study and validation of Turbo decoder and Convolutional decoder (CDMA, WCDMA, EDGE) used in base station SoC. Test developed in C++ for TestBuilder.

2003 : 4 month ACCENT Genoa Italy

Redesign, integration and validation of an ADSL modem.
I used ATM, PCI, USB protocol.

2003 February - Juin : 5 month Internship at STMicroelectronics Grenoble IP and Design center

Study design and synthesis of arithmetic operators for ST100 DSP in order to replace a Full Custom method.

At Grenoble STMicroelectronics, I worked on arithmetic operators design for ST100 DSP-MCU.
I studied the opportunity to use SYNOPSIS DesignWare on high performance design at 400MHz MAC on 130nm technology.

With this work experience, I can learn and practice the design methods of semiconductor industry.
I had to code in RTL VHDL and by the way discover the design flow, simulation on NCSIM, synthesis with Design et Physical Complier by SYNOPSYS.
I had also to practice STA (Static Timing Analysis) to compare my design's performances.

Skills :

· Study of multiplier et adder
· Architectural Study
· VHDL RTL
· Synthesis tool SYNOPSYS Design and Physical Complier
· SYNOPSYS DesignWare
· CADENCE NCSIM

2002 : 300 hour School Project

On this project the aim was to design the electronics to command an autonomous vehicle able to control his motion itself by imaging treatment.

Imaging treatment is done by a DSP TI TMS320C6211. My task was to develop an extension board in order to communicate by CAN Bus and plug and control CMOS Image Sensor via a CPLD.

I chose components, design board and realised routines to exchange data with DSP.

Skills :

· Digital electronics
· Design, build and test of board
· Use developpement board for TI TMS320C6211 (including EMIF and MCBSP peripherals)
· C
· VHDL et CPLD's synthesis
· CAN Bus
· Project management

2000 : L'Entreprise Electrique at Clermont-Ferrand

A month, Installation of cables, automaton for traffic lights and other urban furniture.

1999 : Internship of 10 weeks at l'AIA

Maintenance of French Military Aeronautics in Clermont-Ferrand.
Programming of test bench for electrical flight control of Mirage 2000.

1998 : 2 Months used to improve my english

Employment as Kitchen Porter in STRATFORD VICTORIA HOTEL at STRATFORD UPON AVON England.